The article embraces the issues of effective mapping into the FPGA architecture of the random access memory devices that are parts of application-specific processors’ program models. According to the analysis of modern FPGA architecture, the approaches of effective memory mapping are suggested; methods, algorithms and software means are developed.
Design principles of toolkit for characteristics investigation of the digital signal processors generated by Chameleon© C2HDL design tool and implemented to the FPGA of Altera DE1-SoC platform are considered. The structure and organization of toolkit and its components, including the digital signal processor synthesis and implementation in FPGA flow are described. The chain of DSP performance investigation which are generated by the Chameleon© C2HDL design tool using toolkit is formed.
The paper describes optimization of the greedy algorithm that can be used to optimize the placement / routing between components in computer systems, when the sequences of data were obtained by using combinations. The disadvantages of original greedy algorithm were analyzed and its optimized version, which is based on an ordered matrix notation to store permutation, was proposed. This approach increases algorithm performance in 2.7 times for 482 unique items