A hardware implementation design of parallelized fuzzy Adaptive Resonance Theory neural network is described and simulated. Parallel category choice and resonance are implemented in the network. Continuous-time and discrete-time winner-take-all neural circuits identifying the largest of M inputs are used as the winner-take-all units. The continuous-time circuit is described by a state equation with a discontinuous right-hand side. The discrete-time counterpart is governed by a difference equation.
The design of mathematical models and corresponding functional block-diagrams of discrete-time neural networks for Internet information retrieval, parallel sorting, and rankorder filtering is proposed. The networks are based on the discrete-time dynamical K-winnerstake-all (KWTA) neural circuits which can identify the K largest from N input signals, where 1£ < K N is a positive integer. Implementation prospects of the networks in an up-to date digital hardware are outlined.