Multiplier realization in FPGA of the high level Galois fields.
In this paper, the implementation of matrix multipliers of the Galois fields with basics 2, 3, 5, 7, 13 and the analysis of the implementation of multipliers with a higher basis on the FPGA Xilinx Spartan-6 and Altera – Cyclone-5 is considered. It is shown that the smallest hardware costs will be in multiples of Galois fields with a base 2. For the implementation of the Guild cells with a large foundation, the core generator of the modified Guild cells was implemented.