hardware implementation

Tools for micro-satellite video stream lossless compression

Features of construction of devices for compression of lossless images are considered. The study of the features of the construction allows you to fully understand the principles of these devices and the methods of compression, which underlie their work. JPEG-LS method and CCSDS121.0-B-2 standard are chosen as ways of compression of lossless images. The implementation of these methods with different types of architectures on modern FPGAs is considered. A comparison of the results of the implemented nodes on the FPGA.

Approach to implementation on FPGA of data compression algorithm C language descriptions by the means of VIVADO package

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.

Approach to implementation of JPEG-LS lossless image compression method

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.

Internet Information Retrieval, Parallel Sorting, and Rank-Order Filtering Based on Dynamical Neural Circuits of Maximal Value Signal Identification Among Discrete-Time Signals

The design of mathematical models and corresponding functional block-diagrams of discrete-time neural networks for Internet information retrieval, parallel sorting, and rankorder filtering is proposed. The networks are based on the discrete-time dynamical K-winnerstake-all (KWTA) neural circuits which can identify the K largest from N input signals, where 1£ < K N is a positive integer. Implementation prospects of the networks in an up-to date digital hardware are outlined.

Rank-order filtering based on analogue k-winners-take-all neural circuit

The problem of rank-order filtering is solved on the base of analogue neural circuit which determines maximal value signals among signal set. The filter is described by system of algebra-differential equations and combines such properties as high accuracy and speed, low computational and hardware implementation complexity, and independency on initial conditions. The filter can be used for processing of constant signals, variable signals, and also equal signals. The filter simulation examples confirming theoretical statements are provided.