логічна мінімізація

Efficient Construction of Bitsliced DES S-Boxes With Reduced Logical Complexity

This paper presents a heuristic approach to the synthesis of bitsliced representations of S-Boxes of size n ≥ 5, aimed at minimizing the number of typical processor logic instructions (NOT, OR, XOR, AND, ANDN). The proposed approach provides efficient implementation of such representations on a wide range of processor architectures – from resource-constrained 8/16/32-bit microcontrollers to high-performance 64-bit processors of the x86, ARM and RISC-V architectures, in particular on platforms with vector extensions of the instruction set.

Minimization of BITSLICED-representation of 4×4 s-Boxes based on ternary logic instruction

The article is devoted to methods and tools for generating software-oriented bitsliced descriptions of bijective 4×4 S-Boxes with a reduced number of instructions based on a ternary logical instruction. Bitsliced descriptions generated by the proposed method make it possible to improve the performance and security of software implementations of crypto-algorithms using 4×4 S-Boxes on various processor architectures and when designing encryption hardware.

Heuristic method for bitsliced representation of randomly generated 8×8 cryptographic S-Box

The article is devoted to the issues of increasing the security and efficiency of software implementation for the symmetric block ciphers. For the implementation of cryptoalgorithms on low-end CPUs (8/16/32-bit microcontrollers), it is important to provide increased resistance to power consumption analysis attacks. With regard to the implementation of ciphers on high-end CPUs (x86, ARM Cortex-A), it is important to eliminate the vulnerability primarily to timing and cache attacks.