Efficient Construction of Bitsliced DES S-Boxes With Reduced Logical Complexity
This paper presents a heuristic approach to the synthesis of bitsliced representations of S-Boxes of size n ≥ 5, aimed at minimizing the number of typical processor logic instructions (NOT, OR, XOR, AND, ANDN). The proposed approach provides efficient implementation of such representations on a wide range of processor architectures – from resource-constrained 8/16/32-bit microcontrollers to high-performance 64-bit processors of the x86, ARM and RISC-V architectures, in particular on platforms with vector extensions of the instruction set.