The improvement of noise immunity of a communication system is an effective way to increase the capacity of communication systems, which would provide more qualitative service for a larger number of users. This task can be solved by lowering the noise threshold of a phase-locked loop (PLL) in these systems if the dynamic properties of the device are preserved. The literature review indicates that such a device with improved noise immunity has already been implemented, but the effects of noise and modulation on its dynamic behavior were analyzed separately. This article is devoted to the analysis of the behavior of a digital firmware PLL under the simultaneous influence of noise and modulation of the input signal. The article depicts the structure of the classical digital PLL and its modifications and explains key differences between them.
The simulation of the classical PLL with either absence or presence of noise at the device input was carried out. The simulation results show that the PLL is not able to detect all phase changes when the noise is present. Besides, the modified PLL has a wider working frequency range than the classical one under noisy conditions. The investigations of the PLL dynamic behavior with the simultaneous influence of random noise and Binary Phase Shift Keying (BPSK) modulated input signal was performed. The results of the research show that the duration of the transient processes during the processing of the BPSK modulated signal in the modified device is at least twice as low as that for the classical one. In addition, the number of errors during the signal detection increases faster for the classical PLL than for the modified one when the noise level rises. The use of the modified PLL in modern communication systems gives an opportunity to increase their capacity.
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