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  4. Logical Algorithms of the Accelerated Multiplication With Minimum Quantity of Nonzero Digits of the Converted Multipliers

Logical Algorithms of the Accelerated Multiplication With Minimum Quantity of Nonzero Digits of the Converted Multipliers

ACPS.
2019;
Volume 4, Number 1
: pp. 25 - 31
https://doi.org/10.23939/acps2019.01.025
Authors:
  1. Ivan Korol
  2. Ihor Korol
1
Uzhhorod National University
2
Uzhhorod National University, John Paul II Catholic University of Lublin

The article presents a new algorithm of accelerated multiplication, in which the time of multiplication has been reduced through the decrease in the number of nonzero digits of the multiplier. In this case, the multiplier has been presented in the form of the extended binary code. The article proves the algorithm's efficiency in comparison to previously known methods. The developed algorithm has been implemented using the hardware description language AHDL (Altera Hardware Description Language) in the Logic Development System
MAX+PLUS II.

extended binary code
accelerated multiplication device
AHDL
MAX+plus

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