Optimization of the Algorithm Flow Graph Width in Neural Networks to Reduce the Use of Processor Elements on Single-board Computers

The article presents a method for optimizing the algorithm flow graph of a deep neural network to reduce the number of processor elements (PE) required for executing the algorithm on single-board computers. The proposed approach is based on the use of a structural matrix to optimize the neural network architecture without loss of performance. The research demonstrated that by reducing the width of the graph, the number of processor elements was reduced from 3 to 2, while maintaining network performance at 75% efficiency. This approach is significant as it expands the potential applications of neural networks in embedded systems and IoT, enhancing the efficiency of computational resource utilization on devices with limited computational capabilities, ensuring effective use of resources.