CPU

Minimization of BITSLICED-representation of 4×4 s-Boxes based on ternary logic instruction

The article is devoted to methods and tools for generating software-oriented bitsliced descriptions of bijective 4×4 S-Boxes with a reduced number of instructions based on a ternary logical instruction. Bitsliced descriptions generated by the proposed method make it possible to improve the performance and security of software implementations of crypto-algorithms using 4×4 S-Boxes on various processor architectures and when designing encryption hardware.

Method and utility for minimizing bitsliced representations of 4×4 S-boxes

The article is devoted to methods and tools for generating bitsliced descriptions of bijective 4×4 S-Boxes with a reduced number of gates/instructions. Bitsliced descriptions generated by the proposed method make it possible to improve the security and performance of both software implementations of cryptoalgorithms using 4×4 S-Boxes on various processor architectures, as well as FPGA and ASIC based hardware.