directed acyclic graph

Transfer optimization while adding of binary numbers in number-theoretic basis Rademacher

The mathematical model of computer circuit as directed acyclic graph for the construction of parallel adders with parallel transfer method. Demonstrated communication between computing steps directed acyclic graph and the process of transfer of units in the scheme multibit adder that can determine the optimal number of transfers in the scheme multibit parallel adder with parallel transfer method in theoretical and numerical basis Rademacher. The process of adding binary numbers in the adder circuit uses an algorithm logarithmic summation.