Method of parallelism extraction from sequential program is proposed. The definition of three address code is given. The requirements to the sequential and parallel program are determined. The structure and design performance of the parallel program are given. The description of two stages of the parallelism extraction method is proposed: stage of preliminary field initialization and recursive stage of the parallel extraction. Evaluate efficient of the parallelism extraction method based on an example of FFT 64p.
[1] "Compile Your C code into Verilog", [Online]. Available: http://cto-verilog.com/index.html.
[2] "C-to-FPGA Solutions", [Online]. Available: http://www.impulseaccelerated.com/products_universal.htm.
[3] "Handel-C Synthesis Methodology", [Online]. Available: http://www.mentor.com/products/fpga/handel-c/.
[4] I. Innovations, "CHAMELEON - the System-Level Design Solution", [Online]. Available: http://introninnovations.com/?p=sld_chame.
[5] A. Melnyk, A. Salo, V. Klymenko та L. Tsyhylyk, "Chameleon -system for specialized processors high-level synthesis", Scientifictechnical magazine of National Aerospace University "KhAI" No. 5, pp. 189-195, 2009.
[6] A. Melnyk, A. Salo, "Automatic generation of ASICs", NASA-ISA Conference AHS-2007, pp. 96-101, 2007.
https://doi.org/10.1109/AHS.2007.36
[7] D. Cordes, A. Heinig and P. Marwedel, "Automatic Extraction of Pipeline Parallelism for Embedded Software Using Linear Programming", in IEEE 17th International Conference on Parallel and Distributed Systems, 2011.
https://doi.org/10.1109/ICPADS.2011.31
[8] J. V. Dyken and J. O. Delgado-Frias, "A Medium-Grain Reconfigurable Processor Organization", School of Electrical Engineering and Computer Science,Washington, 2011.
https://doi.org/10.1109/MWSCAS.2011.6026460
[9] A.Melnyk, "Design of SCS", 1996.
[10] L. Tsyhylyk, "Transformation Method of conditional comands in parallel way", Bulletin of National University "Ukraine", pp. 156-159, 2010.
[11] D. Cordes, M. Engel, O. Neugebauer and P. Marwedel, "Automatic Extraction of Pipeline Parallelism for Embedded Heterogeneous Multi-Core Platforms", Dortmund, Germany, 2013.
https://doi.org/10.1109/CASES.2013.6662508
[12] A. Gontmakher, A. Mendelson, A. Schuster and G. Shklover, "Code Compilation for an Explicitly Parallel Register-Sharing Architecture", in International Conference on Parallel Processing, 2007.
https://doi.org/10.1109/ICPP.2007.24
[13] C. Roth, S. Reder, H. Bucher, O. Sander and J. Becker, "Adaptive Algorithm and Tool Flow for Accelerating SystemC on Many-Core Architectures", in 17th Euromicro Conference on Digital System Design, 2014.
https://doi.org/10.1109/DSD.2014.62
[14] T. Bernard; K. Bousias; L. Guang; C. R. Jesshope; M. Lankamp; M. W. van Tol; L. Zhang, "A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors", Institute for Informatics, University of Amsterdam, Amsterdam, Netherlands, 2008.
https://doi.org/10.1109/ICSAMOS.2008.4664840
[15] A. Melnyk and V. Melnyk, Personal Supercomputers: Architecture, Design, Application, Lviv: Lviv National Polytechnic University Publishing, 2013.
[16] L. Yan, B. Wu, Y. Wen, S. Zhang and T. Chen, "A reconfigurable processor architecture combining multi-core and reconfigurable processing unit", in 10th IEEE International Conference on Computer and Information Technology (CIT 2010), 2010.
https://doi.org/10.1109/CIT.2010.484
[17] A. Melnyk and B. Dunets, "FFT Processor IP Cores synthesis on the base of configurable pipeline architecture", CADSM'2003, Lviv- Slasko, 2003.
[18] V. Chandrakanth; Tripathi Srijan, "Customized Architecture For Implementing Configurable FFT on FPGA", 3rd IEEE International Advance ComputingConference (IACC), pp. 1280-1282, 2013.
https://doi.org/10.1109/IAdCC.2013.6514412
[19] Y. Li, Z.-y. Wang, J. Ruan and K. Dai, "Research and Implement a Low-Power Configurable Embedded Processor for 1024-Point Fast Fourier Transform", in School of Computer, National University of Defense Technology, Hunan Changsha, P. R. China, 2007.
https://doi.org/10.1109/ICASIC.2007.4415566
[20] A. Melnyk, I. Yakovleva, V. Uschenko, "Design and Matrix representation of Data Flow Graph", Bulletin of Vinnitsky Polytechnic Institute No. 3, pp. 93-99, 2009.
[21] "C to HDL", 16 September 2014. [Online]. Available: http://en.wikipedia.org/wiki/C_to_HDL.