Ієрархічне острівкування енергетичних мереж

: pp. 15-18
Accepted: February 23, 2016
Lviv Polytechniс National University, Software Department
Lviv Polytechniс National University

The features of using the method of optimal scheme reduction for islanding of power
systems is reviewed. A modified algorithm for series-parallel folding with the formation of
hierarchically nested clusters is offered. The advantages of the algorithm is grounded and its
implementation in the application for islanding of power system is described.

1. Базилевич Р. П. Декомпозиционные и топологические методы автоматизированного проектирования электронных устройств. – Львов: Вища школа, 1981. – 168 с.

2. Bazylevych R. P., Melnyk R. A., Rybak O. G. Circuit partitioning for FPGAs by the optimal circuit reduction method // In: VLSI Design. – 2000. – Vol. 11, No 3. – P. 237–248.

3. Bazylevych R., Podolskyy I. and Bazylevych L. Partitioning optimization by recursive moves of hierarchically built clusters // In: Proc. of 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. April, 2007, Krakow, Poland. – P. 235–238.

4. Peiravi A., Ildarabadi R. Comparison of Computational Requirements for Spectral and Kernel k-means Bisectioning of Power Systems // Australian Journal of Basic and Applied Sciences, 3(3): 2366-2388, 2009.

5. Agematsu S., Imai S., Tsukui R., Watanabe H., Nakamura T., Matsushima T. Islanding Protection System with Active and Reactive Power Balancing Control for Tokyo Metropolitan Power System and Actual Operational Experiences // In Proceedings of the 7th IEE Int. Conf. Developments in Power System Protection. – 2001. – P. 351–354.

6. Cherng, J., Chen S., Tsai C., Ho J., 1999. An efficient two-level partitioning algorithm for VLSI circuits // Proceedings of the 1999 Design Automation Conference, ASP-DAC '99, Asia and Pacific, 1: 69–72, Wanchai, Hong Kong, 18–21 Jan. 1999.

7. Cherng J., Chen S., 2003. An efficient multi-level partitioning algorithm for VLSI circuits // Proceedings of the 16th 70–75. International Conference on V LSI Design (VLSI'03), 4–8 January 2003.

8. Dhillon, Inderjit S., Guan, Yuqiang, Kulis, Brian, 2005. A Fast Kernel Based Multilevel Algorithm for Graph Partitioning // In the Proceedings of the 111th ACM SIGKDD International Conference on Knowledge Discovery Data Mining (KDD). – P. 629–634.

9. Bazylevych R. P. The optimal circuit reduction method as an effective tool to solve large and very large size intractable combinatorial VLSI physical design problems // In: 10-th NASA Symp. on VLSI Design, March 20–21, 2002, Albuquerque, NM, USA. – P. 6.1.1–6.1.14.