Synthesis of Multi-Bit Pyramidal Adders on FPGA
The paper analyses the system characteristics and functional capabilities of multi-bit pyramidal adders that can be used in the structures of discrete perceptron of modern neural networks for summing weight coefficients and input signals. The methodology for designing multi-bit adders using flow and spatial-temporal graphs is described. Algorithmic and recursive pyramidal adders have been developed and their main system characteristics have been determined.