Описується математична модель нейронної схеми типу «K-winners-take-all» (KWTA), призначеної для ідентифікації К максимальних серед N невідомих сигналів, де $1≤K<N$. Аналізується обробка моделлю постійних дискретизованих вхідних сигналів. Розглядається випадок рівних між собою вхідних сигналів. Наводяться відповідні результати комп’ютерного моделювання.
A model of parallel sorting neural network of discrete-time has been proposed. The model is described by system of difference equations and by step functions. The model is based on simplified neural circuit of discrete-time that identifies maximal/minimal values of input data and is described by difference equation and by step functions. A bound from above on a number of iterations required for reaching convergence of search process to steady state is determined. The model does not need a knowledge of change range of input data.
Features of construction of devices for compression of lossless images are considered. The study of the features of the construction allows you to fully understand the principles of these devices and the methods of compression, which underlie their work. JPEG-LS method and CCSDS121.0-B-2 standard are chosen as ways of compression of lossless images. The implementation of these methods with different types of architectures on modern FPGAs is considered. A comparison of the results of the implemented nodes on the FPGA.
The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.
The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.
The design of mathematical models and corresponding functional block-diagrams of discrete-time neural networks for Internet information retrieval, parallel sorting, and rankorder filtering is proposed. The networks are based on the discrete-time dynamical K-winnerstake-all (KWTA) neural circuits which can identify the K largest from N input signals, where 1£ < K N is a positive integer. Implementation prospects of the networks in an up-to date digital hardware are outlined.