A RISC microprocessor architecture that realiz es a specific method of parallelism including the instruction level parallelism has been considered. The processor has been provided for 4-bit data type tag in each register of the register file. There are 14 data type tag values. The zero data type tag indicates that the register is free, otherwise it is busy. The destination register inherits the data type tag from the first source register. After an operation the data type tags in the source registers maybe either zeroed, or may remain unchanged for further usage. Al l machine operations are classified into computational operations (about 40), and auxiliary operations (about 35-45). The computational operations include integer, unsigned, floating point, logical, string, and conversion operations. The processor has specific instruction formats in which there are 6-bit fields both for the operation code and the computational code. A single primary computational instruction having zero in the operation code field, and a meaningful code in the computational code field is enough to express all computational operations. A compiler generates groups of instruct ions to perform in parallel, the reordering of instructions may take place. There are several clones of the primary computational instruction with operation codes differing from zero. A clone computational instruction with a certain operation code is placed as a header instruction for the instruction group pointing out a certain number of instructions in the group to issue in parallel. The primary instructions may be placed inside the groups. The concept of flux is introduced as a composite of stream of instructions and a flow of processed data maintained by the flux hardware. Fluxes improve the usage of mult iple functional units, and may be used for further parallelization.
[1] David A. Patterson and John L. Hennessy. Computer Organization and Design. The Hardware / Software Interface, Fourth edition, Morgan Kaufmann Publishers, 2009, 940 p.
[2] Andrew Waterman, Yunsup Lee, David A. Patterson, Krste Asanović. The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0, Electrical Engineering and Computer Sciences, University of California at Berkeley, 2014, 92 p.
https://doi.org/10.21236/ADA605735
[3] David A. Patterson, «Reduced Instruction Set Computers», in Communications of the ACM, volume 28, Number 1, January, 1985, pp. 8-21.
https://doi.org/10.1145/2465.214917
[4] Joseph D. Dumas II. Computer Architecture. Fundamentals and Principles of Computer Design (University of Tennessee at Chattanooga, Chattanooga, TN, USA), Taylor & Francis Group, LLC, 2017, 450 p.
[5] Dezső Sima, Terry J. Fountain, Péter Kacsuk. Advanced Computer Architectures: A Design Space Approach, Addison-Wesley, 1997, 766 p.
[6] Melnyk A. O. Architecture of Computer. Manual (Lviv Polytech-nic National University), Lutsk regional printing, Ukraine, 2008, 470 p. (МельникА. О. Архітектуракомп'ютера. Підручник).
[7] Korolev, L. N. Architecture of electronic computers, Nauchny mir, Moscow, Russia, 2005, 272 p. (КоролевЛ. Н. Архитектура электронных вычислительных машин, М, Научныймир).
[8] Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, Dean M. Tullsen, «Simultaneous Multithreading: A Platform for Next-Generation Processors», in IEEE Micro, September/October, 1997, pp. 12-19.
https://doi.org/10.1109/40.621209
[9] V. K. Dobrovolskyi, «Microprocessor with Explisit Parallelism», in Proceedings of VIth International Scientific Conference SIMU-LATION-2018 (МОДЕЛЮВАННЯ-2018), September 12-14, 2018, Kyiv, Ukraine, pp. 135-138, ISBN 978-966-02-8587-3.
[10] V. K. Dobrovolskyi, «Microprocessor with Tagged Registers», in Proceedings of the Vth International Scientific Conference Simulation-2016, May 25-27, 2016, Kiev, Ukraine, pp. 57-60, ISBN 978-966-02-7928-5 (file), ISBN 978-966-02-7927-8 (printed edition).
[11] Dobrovolskyi, Volodymyr. Microprocessor with Tagged Registers. Version 1.1, Kyiv, University Publishing House «Pulsary», 2017, 60 p., ISBN 978-617-615-073-2.
[12] Marc Tremblay, Jeffrey Chan, Shailender W. Conigliaro, Shing Sheung Tse, «The MAJC Architecture: A Synthesis of Parallelism and Scalability», in IEEE MACRO, November-December, 2000, pp. 12-25.
https://doi.org/10.1109/40.888700
[13] Iliffe, J. K. Basic Machine Principles, London, MacDonald & Co., 1968, vii+86 p. [14]Instruction operations for the B8501 Central Processing Module. Reference Manual, Burroughs The Corporation, 1966, 101