A hardware implementation in FPGA based reconfigurable computing architecture of discrete-time neural circuit that is capable of identifying the K largest/smallest of any unknown finite value N distinct inputs, where 1 ≤ K < N is presented. The circuit has low computational and hardware implementation complexity, high speed of signal processing, it is capable to process signals of any finite range, possesses signal order preserving property and does not require resetting and corresponding supervisory circuit that increases a speed of signal processing. The hardware implementation based on the results of mathematical modeling KWTA Neural Network with the FPGA-based reconfigurable computing architecture has been described. The issues of using hardware blocks combining VHDL coding have been discussed. Simulation example demonstrating the circuit performance is presented.
1. Lippmann R. P. A comparison of Hamming and Hopfield neural nets for pattern classification / R. P. Lippmann, B. Gold, and M. L. Malpass // MIT Lincoln Laboratory Technical report TR-769 (1987) 1–37. 2. Majani E., Erlanson R. and Abu-Mostafa Y. On the K -winners-take-all network, in: Advances in Neural Information Process. Syst. D. S. Touretzky, Vol. 1 (Kaufmann, San Mateo, 1989) 634–642. 3. Tymoshchuk P. A winner-take-all circuit using neural networks as building blocks / P. Tymoshchuk and E. Kaszkurewicz // Neurocomputing 64 (2005) 375–396. 4. Urahama K. K-Winner-take-all circuit with 0(n) complexity / K. Urahama and T. Nagao // IEEE Trans. on Neural Networks 6 (1995) 776–778. 5. Yen J. C. A new k -Winners-take all neural network and its array architecture / J. C. Yen, J. I. Guo, and H.-C. Chen // IEEE Trans. on Neural Networks 9 (1998) 901–912. 6. Kwon T. M. and Zervakis M. A parallel sorting network without comparators: A neural-network approach, in: Proc. Int. Joint Conf. on Neural Networks, Vol. 1 (1992) 701–706. 7. Bihn L. N. A neural-network contention controller for packet switching networks / L. N. Bihn and H. C. Chong // IEEE Trans. on Neural Networks 6 (1995) 1402–1410. 8. Liu S. A simplified dual neural network for quadratic programming with its KWTA application / S. Liu and J. Wang // IEEE Trans. on Neural Networks, 17 (2006) 1500–1510. 9. DeSouza G. N. Vision for mobile robot navigation: a survey / G. N. DeSouza and A. C. Zak // IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 24, no. 2, pp. 237–267, Feb. 2002. 10. O’Reilly R. C. Computational explorations in cognitive neuroscience: understanding the mind by simulating the brain / R. C. O’Reilly and Y. Munakata. – Cambridge, MA: MIT Press, 2000. 11. A. Lazar Fading memory and time series prediction in recurrent networks with different forms of plasticity / A. Lazar, G. Pipa, and J. Triesch // Neural Networks, vol. 20, № 3, pp. 312–322, Apr. 2007. 12. Wolfe W. J. K-Winner networks / W. J. Wolfe, D. Mathis, C. Anderson, J. Rothman, M. Gotler, G. Bragy, R. Walker, G. Duane, and G. Alaghband // IEEE Trans. on Neural Networks 2 (1991) 310–315. 13. Perfetti R. On the robust design of k-winners-takeall networks / R. Perfetti // IEEE Trans. on Cir. and Syst.-II: Analog and Digit. Sign. Process., CAS-42 (1995) 55–58. 14. Yen J. C. and Chang S. A new first- k -winners neural network, in: Proc. of the ISANN (1997) D-01-D-06. 15. Yang J. F. A Dynamic K-Winners-Take-All Neural Network / J. F. Yang and C. M. Chen // IEEE Trans. on Syst., Man and Cyb. 27 (1997) 523–526. 16. Calvert B. D. Another K -winners-take-all analog neural network / B. D. Calvert and C. A. Marinov // IEEE Trans. on Neural Networks 4 (2000) 829–838. 17. Marinov C. A. Performance analysis for a K -winners-take-all analog neural network: basic theory / C. A. Marinov and B. D. Calvert // IEEE Trans. on Neural Networks 14 (2003) 766–780. 18. Marinov C. A. Stable computational dynamics for a class of circuits with 0(N) interconnections capable of KWTA and rank extractions / C. A. Marinov and J. J. Hopfield // IEEE Trans. on Cir. and Syst. I: Fundamental Theory and Applications 52 (2005) 949–959. 19. Hu X. An improved dual neural network for solving a class of quadratic programming problems and its k-winners-take-all application / X. Hu and J. Wang // IEEE Trans. on Neural Networks, 19 (2008) 2022–2031. 20. Wang J. Analysis and design of a k-winners-take-all model with a single state variable and the Heaviside step activation function / J. Wang // IEEE Trans. Neural Networks, vol. 21, № 9, pp. 1496–1506, Sept. 2010. 21. Тимощук П. Математична модель нейронної схеми типу “K-Winners-Take-All” обробки дискретизованих сигналів / П. Тимощук // Компютерні системи проектування. Теорія і практика. – 2010. – № 685. – С. 45–50. 22. Тимощук П. Оптимізація нейронної схеми ідентифікації максимальних дискретизованих сигналів / П. Тимощук // Оптимізація виробничих процесів і технічний контроль у машинобудуванні та приладобудуванні. – 2010. – № 679. – С. 107–112. 23. Hui-Ya Li Hardware Implementation of k-Winner-Take-All Neural Network with On-Chip Learning / Hui-Ya Li, Chien-Min Ou // 13th IEEE International Conference on Computational Science and Engineering, 2010. 24. Cichocki A. Neural Networks for Optimization and Signal Processing / A. Cichocki and R. Unbehauen. – New York: John Wiley and Sons, 1993. 25. Sahoolizadeh H. A FPGA implementation of neural/wavelet face detection system / Sahoolizadeh H., & Keshavarz A. // Australian Journal of Basic and Applied Sciences, 2010. – 4(3), 379–388. 26. Reyneri L. M. Implementation issues of neuro-fuzzy hardware: going towards HW/SW codesign / Reyneri L. M. // IEEE Transactions on Neural Networks, 2003. – 14(1), 176–194. 27. Muthuramalingam A. Neural network implementation using FPGA: issues and application / Muthuramalingam A., Himavathi S., & Srinivasan E. // International Journal of Information Technology, 2008. – 4:2, 95–101. 28. Krips M. FPGA implementation of a neural network for a real-time hand tracking system / Krips M., Lammert T., & Kummert A. // Proceedings of the 1st IEEE International Workshop on Electronic Design, Test and Applications, 2002. – 29–31, 313–317. 29. Lin C.-J. FPGA implementation of a recurrent neural fuzzy network with on-chip learning for prediction and identification applications / Lin C.-J., & Lee C.-Y. // Journal of Information Science and Engineering, 2010. – 25, 575– 589. 30. Zheng M. FPGA implementation of a neural network control system for a helicopter / Zheng M., Tarbouchi M., Bouchard D., & Dunfield J. // Proceedings of the 7th WSEAS International Conference on Neural Networks, 2006. – 7–10. 31. Haitham K. A. Design artificial neural network using FPGA / Haitham K. A., & Esraa Z. M. // IJCSNS International Journal of Computer Science and Network Security, 2010. – 10(8), 88–92. 32. Muthuramalingam A. Neural Network Implementation Using FPGA: issues and Application / A. Muthuramalingam, S. Himavathi, E. Srinivasan // Intarnational Journal of Information Technology, 2008. 33. Ali H. Design Artificial Network Using FPGA / H. Ali, E. Mohammed // IJCSNS International Journal of Computer Science and Network Security. – 2010. – vol. 10, № 8.