The problem of optimizing finite impulse response (FIR) digital filters is relevant in the context of limited computational resources of embedded systems. Existing methods for implementing FIR filters often lead to significant energy consumption and processing time, which limits their application in real-world conditions. The objective of this work is to develop methods for optimizing FIR filters to reduce computational complexity and ensure efficient operation on embedded systems with limited resources. The research methodology includes the analysis of structurally optimized filter circuits, in particular multi-stage and block configurations, as well as the use of algorithms to reduce the bit depth of coefficients. The results of the study show that the proposed approaches can significantly reduce computational cost and power consumption without sacrificing filter quality. The novelty of the work lies in the combination of structural optimization methods with algorithmic techniques that consider the peculiarities of hardware implementation on embedded systems. The practical significance of the work lies in the possibility of using optimized filters for real-time signal processing on devices with limited resources. Directions for further research include studying the effectiveness of the optimization methods on different platforms, such as FPGAs and microcontrollers, as well as adaptation to different types of signals.
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