Research and Design of a Matrix Multiplier on Fpga
This paper presents a comprehensive investi- gation and hardware implementation of a multi-bit Brawn matrix multiplier architecture. The research focuses on analyzing the system characteristics of binary multipliers realized with both conventional and optimized full and half adders. Particular attention has been given to the applicability of such multipliers within arithmetic logic units (ALUs) for vector and scalar processing architectures. Analytical models have been formulated to quantify hardware resource utilization and computational latency across various logic base configurations.