This article is devoted to the creation of a firmware implementation of the digital phase- locked loop (DPLL). DPLLs are more perspective than analog PLLs in terms of reliability and technical characteristics. Moreover, DPLLs potentially have better noise immunity than analog ones.
Advantage of the firmware implementation of the DPLL is its flexibility in configuration. So, the creation of such implementation gives a possibility to speed up further investigation of DPLL noise immunity.