Firmware Implementation of Digital Phase-Locked Loop

: pp. 83 - 90
Lviv Polytechnic National University
Lviv Polytechnic National University, Department of Theoretical Radio Engineering and Radio Measurement

This article is devoted to the creation of a firmware implementation of the digital phase- locked loop (DPLL). DPLLs are more perspective than analog PLLs in terms of reliability and technical characteristics. Moreover, DPLLs potentially have better noise immunity than analog ones.

Advantage of the firmware implementation of the DPLL is its flexibility in configuration. So, the creation of such implementation gives a possibility to speed up further investigation of DPLL noise immunity.

The article describes the block diagram of the DPLL and explains its principle of operation. Furthermore, this article presents mathematical models of all building blocks of the DPLL, including their transfer functions and difference equations. In addition, there are deducted the formulas for digital filter coefficients on the basis of a location of poles and zeros of the DPLL transfer function.

The block diagram of hardware part of the DPLL implementation is also presented. It is built on STM microcontroller and a PC (personal computer), which is connected to it in order to collect data during an operation of the DPLL. The algorithm of software part of the DPLL implementation is depicted in this paper as well.

In order to prove an ability of work of created firmware implementation the frequency acquisition process of harmonic oscillation is investigated. The paper shows diagrams of DPLL key signals. Experimental results were collected and compared with investigation results of existing simulation model of this DPLL. Their comparison demonstrates full accordance of experimental (firmware) and simulation models of the DPLL.

1. Best R. E. (2003), Phase-locked loops: design, simulation, and applications (professional engineering)., 5th ed., New York, McGraw-Hill Companies Inc. — 436 p. 2. Klinefelter A. (2010), “A Fast- Locking, Sub-Threshold ADPLL Clock Synthesizer for Wireless Sensor Applications”, University of Virginia, available at:,(accessed 5 April 2016). 3. Parmar K. (2014), “All Digital Phase Locked Loop design for different applications: A Review”, IJIRT, Volume 1 Issue 8, pp. 96–99. 4. Silicon Laboratories, “Introduction to FPGA-based ADPLLs” (2011), Silicon Laboratories web-site, available at:,(accessed 5 April 2016). 5. STMicroelectronics (2015), “Reference manual STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx advanced ARM-based 32-bit MCUs”, available at:, (accessed 1 May 2016). 6. Теория и практика цифровой обработки сигналов, “Цифровой контур ФАПЧ (digital PLL) и его свойства”, available at:, (accessed 15 April 2016).