It is shown that for the processing of intensive data flows in industry (management of technological processes and complex objects), energy (optimization of load in power grids), military affairs (technical vision, mobile robot traffic control, cryptographic data protection), transport (traffic management and engine), medicine (disease diagnosis) and instrumentation (pattern recognition and control optimization) the real-time hardware neural networks with high efficiency of equipment use should be applied. The operational basis of neural networks is formed and the following operations are chosen for hardware implementation: the search of the maximum and minimum values, calculation of the sum of squares of differences and scalar product. Requirements for hardware components of neural networks with coordinated vertical-parallel data processing are determined, the main ones of which are: high efficiency of equipment use, adaptation to the requirements of specific applications, coordination of input data intensity with the computation intensity in hardware component, real-time operation, structural focus on VLSI implementation, low development time and low cost. It is suggested to evaluate the developed hardware components of neural networks according to the efficiency of the equipment use, taking into account the complexity of the component implementation algorithm, the number of external interface pins, the homogeneity of the component structure and relationship of the time of basic neuro-operation with the equipment costs. The main ways to control the intensity of calculations in hardware components are the choice of the number and bit rates of data processing paths, changing the duration of the work cycle by choosing the speed of the element base and the complexity of operations implemented by the conveyor. The parallel vertical-group data processing methods are proposed for the implementation of hardware components of neural networks with coordinated parallel-vertical control processing, they provide control of computational intensity, reduction of hardware costs and VLSI implementation. A parallel vertical-group method and structure of the component of calculation of maximum and minimum numbers in arrays are developed, due to parallel processing of a slice from the group of digits of all numbers it provides reduction of calculation time mainly depending on bit size of numbers. The parallel vertical-group method and structure of the component for calculating the sum of squares of differences have been developed, due to parallelization and selection of the number of conveyor steps it ensures the coordination of input data intensity with the calculation intensity, real-time mode and high equipment efficiency. The parallel vertical-group method and structure of scalar product calculation components have been developed, the choice of bit processing paths and the number of conveyor steps enables the coordination of input data intensity with calculation intensity, real-time mode and high efficiency of the equipment. It is shown that the use of the developed components for the synthesis of neural networks with coordinated vertical-parallel data processing in real time will reduce the time and cost of their implementation.
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