The current stage of development of information technology is characterized by the expansion of the applications, much of which is associated with the accumulation of large data sets and parallel data searching in real-time. Such applications include automated systems for multi-level control of technological processes and complex objects, where at the lower levels of such systems is the accumulation of large data sets and their processing in real time. The main source in these systems are different sensors and devices that generate telemetric data. That is why it is very crucial to preprocess this data in real-time for finding further issues. One of the optimal ways for implementing it, is to use hardware approach like programmable logic device (PLD) with FPGA type. For resolving this issue in the article were analyzed the recent research and publications and has shown that the disadvantage of existing methods and algorithms for finding the maximum and minimum numbers in one-dimensional and two-dimensional arrays is that they are not focused on hardware implementation by using PLD with FPGA type. It is shown that the development of high-speed hardware for finding maximum and minimum numbers in one-dimensional and two-dimensional arrays should be carried out with an integrated approach, which includes methods, algorithms, structures and modern LPD and should be based on the following principles: homogeneity and regularity of structure; localization and simplification of connections between elements; modularity of construction; pipeline and spatial parallelism of data processing; consistency of the intensity of the discharge of bit sections with the intensity of their processing in the device. The basic operations for the implementation of algorithms for vertical-parallel search of maximum and minimum numbers in one-dimensional and two-dimensional arrays are highlighted and it is shown that they are based on the same type of basic operations with local and regular connections. In the article was developed the method of vertical-parallel searching of maximum and minimum numbers in arrays, which due to parallel processing of the first bit of an array of numbers and parallel formation of control words provides reduction of search time, which is mainly determined by bit numbers. Improved vertical-parallel method of simultaneous search of maximum and minimum numbers in two-dimensional arrays, which due to the simultaneous processing of p one-dimensional arrays and the use of the displacement method reduces the search time by p times compared to the existing method. It is shown that the time of vertical-parallel search of maximum and minimum numbers in one-dimensional and two-dimensional arrays is determined by the bit size of numbers, not their numbers. It is determined that the use of a common bus for formatting of the i-th bit of the maximum (minimum) number and the parallel formation of control words provides an increasing in the processing frequency of bit slices of one-dimensional array. It is determined that the amount of FPGA hardware resources that required for implementation a device for vertical-parallel searching of maximum and minimum numbers in a one-dimensional array mainly depends on the size of the array of numbers, and search time on their bit size.
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