The article presents a new algorithm of accelerated multiplication, in which the time of multiplication has been reduced through the decrease in the number of nonzero digits of the multiplier. In this case, the multiplier has been presented in the form of the extended binary code. The article proves the algorithm's efficiency in comparison to previously known methods. The developed algorithm has been implemented using the hardware description language AHDL (Altera Hardware Description Language) in the Logic Development System

MAX+PLUS II.

[1] Melnyk A.O. Computer Architecture, Lutsk, 2008. – 470 p. (in Ukrainian).

[2] Melnyk A.O., Melnyk V.A. Personal computers: architecture, design, application, Lviv, 2013. – 516 p.

[3] Knuth, Donald E. The Art of Computer Programming, 3rd ed. Reading , MA: Addison-Wesley, 1998. – 762 p.

[4] Korniichuk V.I., Tarasenko V.P., Tarasenko-Kliatchenko O.V. Basics of Computer Arithmetic, Kyiv, 2006. – 164 p. (in Ukrainian).

[5] Tsmots I.G. Parallel algorithms and matrix VLSI structures of multiplication devices for real-time computer systems. Infornation Technologies and Systems. Lviv, 2004. V. 7. N 1, pp. 5-16.