Self-Configurable FPGA-Based Computer Systems: Basics and Proof of Concept

: pp. 39 - 50
Viktor Melnyk

Computer systems performance is today improved with two major approaches: general-purpose computer computing power increase (creation of multicore processors, multiprocessor computer systems, supercomputers), and adaptation of the computer hardware to the executed algorithm (class of algorithms). The last approach often provides application of hardware accelerators – ASIC-based and FPGA-based, also named reconfigurable, and is characterized by better performance / power consumption ratio and lower cost as compared to the general-purpose computers of equivalent performance. However, such systems have typical problems. The ASIC-based accelerators: 1) they are effective only for certain classes of algorithms; 2) for effective application there is a need to adapt algorithms and software. The FPGA-based accelerators and reconfigurable computer systems (that use FPGAs as a processing units): 1) the need in the process of writing a program to perform computing tasks balancing among the general-purpose computer and FPGA; 2) the need of designing applicationspecific processors soft-cores; and 3) they are effective only for certain classes of problems, for which applicationspecific processors soft-cores were previously developed. This paper covers the scope of questions regarding concept of design, architecture, and proof of concept of the Self-Configurable FPGA-Based Computer Systems – an emerging type of high-performance computer systems, which are deprived of specified challenges. The method of information processing in reconfigurable computer systems and its improvements that allow an information processing efficiency to increase are shown. These improvements are used as a base for creating a new type of high-performance computer systems with reconfigurable logic, which are named self-configurable ones, and a new method of information processing in these systems. The structure of self-configurable FPGA-based computer system, the rules of application of computer software and hardware means necessary for these systems implementation are described. Major processes on the stages of program loading and execution in the self-configurable computer system are studied, and their durational characteristics are determined. On the basis of these characteristics, the expressions for evaluating the program execution duration in the self-configurable computer system are obtained. The directions for further works are discussed.

  1. Melnyk, A., Melnyk, V., "Self-Configurable FPGA-Based Computer Systems" Advances in Electrical and Computer Engineering, vol. 13, no. 2, pp. 33-38, 2013, doi:10.4316/AECE.2013.02005. [Online]. Available:
  2. Melnyk, V., Stepanov, V., Sarajrech, Z., "System of load balancing between host computer and reconfigurable accelerator", Proceedings "Computer systems and components" of Tchernivtsi National University. - Tchernivtsi, 2012. - T. 3. Ed. 1. pp. 6-16.
  3. A Proven EDA Solutions Provider makes all the difference. [Online]. Available:
  4. Xilinx Core Generator. Xilinx Inc. [Online]. Available: - 2005.
  5. Melnyk, A, Melnyk, V. "Organization of libraries of standardized and custom IP Cores for high-performance hardware accelerators", Proceedings of IV-th all-Ukrainian conference "Computer Technologies: Science and Education", Ukraine, Lutsk, 9-11 October 2009. - P. 113-117.
  6. Genest, G. "Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C", Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference, 5-8 Aug. 2007. - P. 280-286.
  7. Chameleon - the System-Level Design Solution. [Online]. Available:
  8. ANSI-C to VHDL Compiler. [Online]. Available:
  9. Ivor Horton. Beginning Visual C++ 2005. - John Wiley & Sons, 2005. - 1224 p.
  10. DRC Computer Corporation. RPU100-L60 DRC Reconfigurable Processor Unit. A breakthrough in coprocessor technology. [Online]. Available: pdfs/DRC_RPU100_datasheet.pdf.
  11. H100 Series FPGA Application Accelerators. Version 1.9. September 2008. [Online]. Available: http://www.skyblue. de/nallatech/5595.pdf.
  12. Celoxica Ltd. RCHTX-XV4 High Performance Computing (HPC) Application Acceleration Board Datasheet. Version 1.0. 2006. [Online]. Available: docs/tech/rchtx_datasheet_screen.pdf.
  13. Relogix Assembler-to-C translator. [Online]. Available:
  14. Melnyk, A., Salo, A., Klymenko, V., Tsyhylyk, L. "Chameleon - system for specialized processors high-level synthesis", Scientific-technical magazine of National Aerospace University "KhAI", Kharkiv, 2009. Nо. 5, pp. 189-195.
  15. Handel-C Language Reference Manual For DK Version 4. Celoxica Limited, 2005. - 348p.
  16. Agility Compiler for SystemC. Electronic System Level Behavioral Design & Synthesis Datasheet. 2005. [Online]. Available:
  17. C-to-FPGA Tools form Impulse Accelerated Technologies. Impulse CoDeveloper C-to-FPGA Tools. [Online]. Available:
  18. - Storage Reviews. [Online]. Available:
  19. Read Throughput Maximum: h2benchw 3.16. [Online]. Available: charts-2012/-02-Read-Throughput-Maximum-h2benchw-3.16, 2900.html.
  20. Whitepaper. New SATA Spec Will Double Data Transfer Rates to 6 Gbit/s. SATA-IO. May 27, 2009. [Online]. Available:
  21. DDR4 SDRAM - Micron Technology, Inc. DDR4-Packing Power and Performance into a New Generation. [Online]. Available:
  22. Platform Flash XL High-Density Configuration and Storage Device. Product Specification. DS617 (v3.0.1) January 07, 2010, - 88р. [Online]. Available: documentation/data_sheets/ds617.pdf.
  23. Platform Flash XL Configuration and Storage Device User Guide. UG438 (v2.0) December 14, 2009, - 74 p. [Online]. Available: user_guides/ug438.pdf.
  24. Eric Crabill. Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications. Application Note: Spartan-3 Generation Family. XAPP457 (v1.0) June 8, 2007, Xilinx, Inc. - 9 р. [Online]. Available:
  25. Spartan-3 Generation Configuration User Guide. Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families. UG332 (v1.6), October 26, 2009, Xilinx, Inc. - 352 р. [Online]. Available: user_guides/ug332.pdf.
  26. Virtex-6 FPGA Configuration User Guide // UG360 (v3.5) September 11, 2012, Xilinx, Inc. - 182 р. [Online]. Available: 360.pdf.
  27. Spartan-3E FPGA Family Data Sheet. Product Specification. DS312 October 29, 2012, Xilinx, Inc. - 182 р. [Online]. Available: data_sheets/ds312.pdf.
  28. Melnyk, V. "Principles of construction and operation of reconfigurable computer systems", Scientific journal "Technical Sciences" of Khmelnytskyj National University, Ukraine. - No. 6. - 2012. - P. 212-217.
  29. Koch, D., Beckhoff, C., and Teich, J. "Bitstream decompression for high speed FPGA configuration from slow memories", Proceedings of International Conference on Field-Programmable Technology (ICFPT'07). IEEE, 2007. - P. 161-168.
  30. PassMark AppTimer - Measure application startup time. [Online]. Available: products/apptimer.htm.