A Model of Parallel Sorting Neural Network of Discrete-time

: pp. 67 - 72
Lviv Polytechnic National University, Department of Computer Aided Design Systems

A model of parallel sorting neural network of discrete-time is presented. The model is described by a system of differential equations and by step functions. The network has high speed, any finite resolution of input data and it can process unknown input data of finite values located in arbitrary finite range. The network is characterized by moderate computational complexity and complexity of hardware implementation. The results of computer simulation illustrating the efficiency of the network are provided.

  1. D. E. Knuth, The Art of Computer Programming, Sorting, and Searching. Reading, MA: Addison-Wesley, 1973.
  2. S. G. Akl, Parallel Sorting Algorithms, Orlando, FL: Academic, 1985.
  3. M. Atkins, “Sorting by Hopfield nets,” in Proc. Int. Joint Conf. Neural Netw., Washington, DC, USA, 1989, pp. 65-68.
  4. Y. Takefuji and K.-S. Lee, “A super parallel sorting algorithm based on neural networks,” IEEE Trans. Circuits Syst., vol. CAS-37, no. 11, pp.1425-1429, 1990.
  5. W. Chen and K. Hsieh, “A neural sorting network with O(1) time complexity,” in Proc. Int. Joint Conf. Neural Networks, vol. III, San Diego, CA, 1990, pp. 793-798.
  6. T. M. Kwon and M. Zervakis, “A parallel sorting network without comparators: A neural network approach,” in Proc. Int. Joint Conf. Neural Networks, vol. I, Baltimore, MD, 1992, pp. 701-706.
  7. Y.-H. Tseng and J.-L. Wu, “Solving sorting and related problems by quadratic perceptrons.” Electron. Lett., vol. 28, no. 10, pp. 906-908, 1992.
  8. J. Wang, “Analysis and design of an analog sorting network,” IEEE Trans. Neural Networks, vol. 6, no. 4, pp. 962–971, Jul. 1995.
  9. T. M. Kwon and M. Zervakis, “KWTA networks and their applications,” Multidimensional Syst. and Signal Processing, vol. 6, no. 4, pp. 333-346, Oct. 1995.
  10. J. Wang, “Analysis and design of a k-winners-take-all model with a single state variable and the Heaviside step activation function,” IEEE Trans. Neural Networks, vol. 21, no. 9, pp. 1496-1506, Sept. 2010.
  11. H. M. Alnuweiri and V. K. P. Kumar, “Optimal VLSI sorting with a reduced number of processors,” IEEE Trans. Comput., vol. C-40, pp. 105-110, 1991.
  12. S. Rovetta and R. Zunino, “Minimal-connectivity programmable circuit for analog sorting,” IEE Proc. Circuits, Devices Syst., vol. 146, no. 3, pp. 108-110, Aug. 1999.
  13. P. V. Tymoshchuk and S. V. Shatnyi, “Hardware implementation design of analog sorting neural network”, in Proc. XX Int. Seminar/Workshop “Direct and inverse problems of electromagnetic and acoustic wave theory”, pp. 168-171, Sept. 2015.
  14. P.V.Tymoshchuk, “A discrete-time dynamic K-winners-take-all neural circuit”, Neurocomputing, vol. 72, 2009, pp. 3191-3202.