FPGA

Development of Mobile Facilities of Neuro-like Cryptographic Encryption and Decryption of Data in Real Time

The requirements are formed, the method is chosen and the main stages of development of mobile means of neuro-like cryptographic encryption and real-time data decryption are considered. It is shown that the development of mobile means of neuro-like cryptographic encryption and decryption of real-time data with high efficiency of equipment is reduced to minimize hardware costs while providing a variety of requirements, characteristics and limitations. The tabular-algorithmic method of calculating the scalar product has been improved.

Implementation of Fpga-based Pseudo-random Words Generator

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level.

Parallel Combining Different Approaches to Multi-pattern Matching for Fpga-based Security Systems

The multi-pattern matching is a fundamental technique found in applications like a network intrusion detection system, anti-virus, anti-worms and other signature- based information security tools. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore’s law, traditional software solutions can no longer keep up. Therefore, hardware approaches are frequently being used by developers to accelerate pattern matching.

Tools for micro-satellite video stream lossless compression

Features of construction of devices for compression of lossless images are considered. The study of the features of the construction allows you to fully understand the principles of these devices and the methods of compression, which underlie their work. JPEG-LS method and CCSDS121.0-B-2 standard are chosen as ways of compression of lossless images. The implementation of these methods with different types of architectures on modern FPGAs is considered. A comparison of the results of the implemented nodes on the FPGA.

Approach to implementation on FPGA of data compression algorithm C language descriptions by the means of VIVADO package

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.

Approach to implementation of JPEG-LS lossless image compression method

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.

Satellite Scientific Data Collection and Accumulation system as a Basis for Cyber-Physical Systems Construction

The paper reviews technologies of computer systems the development of which has led to the emergence of cyber-physical systems – there are embedded computer systems, open systems interconnection model, multilayer computer systems, wireless communications, microelectromechanical systems, data protection technologies. It is noted that there are computer systems exist, whose parameters are close to those of cyber-physical systems ones, there are also groups of developers who have experience of in such systems designing. The satellite scientific data collection and

Optimization of Memory Mapping Into Fpga Architecture for Specialized Processors' Program Models

The article embraces the issues of effective mapping into the FPGA architecture of the random access memory devices that are parts of application-specific processors’ program models. According to the analysis of modern FPGA architecture, the approaches of effective memory mapping are suggested; methods, algorithms and software means are developed.

Hardware multitasking in computer systems based on partially reconfigurable FPGAS.

In the article the basic principles of hardware multitasking in the reconfigurable computer systems, based on partially reconfigurable FPGAs, are identified. The structure of the platform to implement hardware multitasking in partially reconfigurable FPGA is proposed. The concept of Virtual Hardware and the questions of the context switch and task relocation in partially reconfigurable FPGA are disclosed.