FPGA

Research and Design of Multibit Binary Adders on Fpga

This paper provides an analysis of the system characteristics and functional capabilities of various types of adders for the high-speed component construction of arithmetic and logical devices in modern superscalar processors. The main features of parallel prefix adders (Sklansky, Brent Kung, Kogge Stone, Ladner Fisher, Han Carlson) and tree-like structures based on incomplete binary adders have been determined in this study. The structures of typical and improved incomplete binary adders have been shown and their complexity characteristics have been calculated as well.

Digital Division Algorithms for Efficient Execution on Integrated Circuits

In this paper, we analyse division algorithms for use on chips and propose the implementation of an optimal divider for these chips. By “optimal”, we refer to an algorithm that meets the following criteria: space efficiency – which involves minimizing resource utilization on the IC’s die area; speed efficiency – the algorithm's processing time (measured in n clock cycles); power efficiency – power consumption of the divider; implementation time – time for implementation of the algorithm using HDL.

Організація хмарних обчислень на базі масиву програмованих комірок логіки

Запропоновано нову хмарну модель обчислень — ПЛІС як послуга, що покликана забезпечити масове використання ПЛІС для організації високопродуктивних обчислень.

New cloud computing model — FPGA as a Service is offered, that called to provide more mass use of FPGA for high-performance computing.

Development of Mobile Facilities of Neuro-like Cryptographic Encryption and Decryption of Data in Real Time

The requirements are formed, the method is chosen and the main stages of development of mobile means of neuro-like cryptographic encryption and real-time data decryption are considered. It is shown that the development of mobile means of neuro-like cryptographic encryption and decryption of real-time data with high efficiency of equipment is reduced to minimize hardware costs while providing a variety of requirements, characteristics and limitations. The tabular-algorithmic method of calculating the scalar product has been improved.

Implementation of Fpga-based Pseudo-random Words Generator

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level.

Parallel Combining Different Approaches to Multi-pattern Matching for Fpga-based Security Systems

The multi-pattern matching is a fundamental technique found in applications like a network intrusion detection system, anti-virus, anti-worms and other signature- based information security tools. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore’s law, traditional software solutions can no longer keep up. Therefore, hardware approaches are frequently being used by developers to accelerate pattern matching.

Tools for micro-satellite video stream lossless compression

Features of construction of devices for compression of lossless images are considered. The study of the features of the construction allows you to fully understand the principles of these devices and the methods of compression, which underlie their work. JPEG-LS method and CCSDS121.0-B-2 standard are chosen as ways of compression of lossless images. The implementation of these methods with different types of architectures on modern FPGAs is considered. A comparison of the results of the implemented nodes on the FPGA.

Approach to implementation on FPGA of data compression algorithm C language descriptions by the means of VIVADO package

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.

Approach to implementation of JPEG-LS lossless image compression method

The features of devices for monochrome images lossless compression by JPEG-LS method in modern element base are discussed. Capabilities of Vivado package (Xilinx) for JPEG-LS algorithm C to suitable for implementation in FPGAs VHDL-descriptions transformation were tested and described. C language structures, which can not be processed by specified means and possible circumvention of such structures were defined.