The article embraces the issues of effective mapping into the FPGA architecture of the random access memory devices that are parts of application-specific processors’ program models. According to the analysis of modern FPGA architecture, the approaches of effective memory mapping are suggested; methods, algorithms and software means are developed.
In the article the basic principles of hardware multitasking in the reconfigurable computer systems, based on partially reconfigurable FPGAs, are identified. The structure of the platform to implement hardware multitasking in partially reconfigurable FPGA is proposed. The concept of Virtual Hardware and the questions of the context switch and task relocation in partially reconfigurable FPGA are disclosed.
Design principles of toolkit for characteristics investigation of the digital signal processors generated by Chameleon© C2HDL design tool and implemented to the FPGA of Altera DE1-SoC platform are considered. The structure and organization of toolkit and its components, including the digital signal processor synthesis and implementation in FPGA flow are described. The chain of DSP performance investigation which are generated by the Chameleon© C2HDL design tool using toolkit is formed.
The article gives an overview of FPGA partial reconfiguration approach and shows the mechanism of its realization. Based on the summarizing and complementing of the existing methodological and design recommendations, a methodological basics of computer devices design for the partially reconfigurable FPGAs is formulated. The design features of the computer devices with undetermined reconfigurable modules are highlighted.
An efficiency of the application-specific processors (ASP) optimization design using C2HDL Chameleon tool and Altera IDE is explored. ASP optimization design supposes to perform the following actions: the set of ASP IP cores synthesis, their FPGA implementation and comparative analysis, optimal version selection according to given criterion.
In the article the structure of the designed FPGA based mobile robot technical system is described. For the design the block-hierarchical approach was used. This system includes the following elements: — the MicroBlaze soft, which is a 32-bit programmable RISC processor with Harvard architecture, in which the processor has separated memory commands and data memory, motor control subsystem, video processing subsystem, radio module control subsystem, sensor control subsystem, the subsystem of obstacle identification.