FPGA

The paper analyses the system characteristics and functional capabilities of multi-bit pyramidal adders that can be used in the structures of discrete perceptron of modern neural networks for summing weight coefficients and input signals. The methodology for designing multi-bit adders using flow and spatial-temporal graphs is described. Algorithmic and recursive pyramidal adders have been developed and their main system characteristics have been determined.

This article proposes three methods for parallelizing the compression of video streams from Earth surface scanners installed on microsatellites. The core innovation lies in the application of vertical, horizontal, and block-based segmentation of the input stream to enable scalable and high-throughput image compression. The study establishes a quantitative relationship between video stream intensity and satellite parameters, and also determines the required number of compression cores based on the satellite's characteristics and the performance of a single core.

This paper presents a comprehensive investi- gation and hardware implementation of a multi-bit Brawn matrix multiplier architecture. The research focuses on analyzing the system characteristics of binary multipliers realized with both conventional and optimized full and half adders. Particular attention has been given to the applicability of such multipliers within arithmetic logic units (ALUs) for vector and scalar processing architectures. Analytical models have been formulated to quantify hardware resource utilization and computational latency across various logic base configurations.

The article explores the possibilities of implementing the JPEG-LS image compression algorithm on Field Programmable Gate Arrays (FPGA) for processing monochrome video streams from Earth surface scanners. A comparison of software implementations of the algorithms, their compression ratio, and execution time is conducted. Methods for improving FPGA performance are considered, using parallel data processing and optimized data structures to accelerate compression and decompression processes.

This paper provides an analysis of the system characteristics and functional capabilities of various types of adders for the high-speed component construction of arithmetic and logical devices in modern superscalar processors. The main features of parallel prefix adders (Sklansky, Brent Kung, Kogge Stone, Ladner Fisher, Han Carlson) and tree-like structures based on incomplete binary adders have been determined in this study. The structures of typical and improved incomplete binary adders have been shown and their complexity characteristics have been calculated as well.

In this paper, we analyse division algorithms for use on chips and propose the implementation of an optimal divider for these chips. By “optimal”, we refer to an algorithm that meets the following criteria: space efficiency – which involves minimizing resource utilization on the IC’s die area; speed efficiency – the algorithm's processing time (measured in n clock cycles); power efficiency – power consumption of the divider; implementation time – time for implementation of the algorithm using HDL.

Запропоновано нову хмарну модель обчислень — ПЛІС як послуга, що покликана забезпечити масове використання ПЛІС для організації високопродуктивних обчислень.

New cloud computing model — FPGA as a Service is offered, that called to provide more mass use of FPGA for high-performance computing.

The goal of the publication is to test the random codes generator of the built-in crypto-protection system

The requirements are formed, the method is chosen and the main stages of development of mobile means of neuro-like cryptographic encryption and real-time data decryption are considered. It is shown that the development of mobile means of neuro-like cryptographic encryption and decryption of real-time data with high efficiency of equipment is reduced to minimize hardware costs while providing a variety of requirements, characteristics and limitations. The tabular-algorithmic method of calculating the scalar product has been improved.

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level.