This work is devoted to the study of the features of the implementation of recurrent logarithmic analog-to-digital converters (LADC). The general principles of construction of recurrent LADCs are outlined. The implementation of recurrent LADC with a constant and a variable in the process of converting the base of the logarithm is considered. Generalized structural schemes of the recurrent LADCs are given, and their accuracy and speed of operation are evaluated. Changing the base of the logarithm leads to a significant increase in the speed of the recurrent LADCs, and it is advisable to change the base according to the binary law. An increase in the number of conversion cycles in the recurrent LADCs with a variable base of the logarithm made it possible to obtain an accuracy higher than the nominal value of the source code. For example, in the 8-bit recurrent LADC, the accuracy of 10 binary digits is obtained in 4 conversion cycles. Exceeding the nominal value by more than 2-4 binary digits is practically impractical due to a significant increase in conversion time.
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