Hardware multitasking in computer systems based on partially reconfigurable FPGAS.

: pp. 83 - 93

Melnyk V.

Національний університет “Львівська політехніка”, кафедра безпеки інформаційних технологій

In the article the basic principles of hardware multitasking in the reconfigurable computer systems, based on partially reconfigurable FPGAs, are identified. The structure of the platform to implement hardware multitasking in partially reconfigurable FPGA is proposed. The concept of Virtual Hardware and the questions of the context switch and task relocation in partially reconfigurable FPGA are disclosed.

1. Top 500 project. "Operating system Family share for 11/2014". [Електронний ресурс]. – Режим доступу: http://www.top500.org/statistics/overtime/. 2. "Embedded market study – Mars, 2012". [Електронний ресурс]. – Режим доступу: http://seminar2.techonline.com/~additionalresources/esd_ apr2012/ubme_embeddedmarket2012_full.pdf. 3. "RTOS market". NewTechPress. November 2011. [Електронний ресурс]. – Режим доступу: http://www.newtechpress.net/2011/11/08/rtos-market-in-turmoil/. 4. [Електронний ресурс]. – Режим доступу: http://blog.tsunanet.net/2010/11/how-long-does-it-take-tomake-context.html. 5. [Електронний ресурс]. – Режим доступу: http://www.linfo.org/context_switch.html. 6. [Електронний ресурс]. – Режим доступу: https://technet.microsoft.com/en-us/library/cc938606.aspx. 7. Brebner G. J. A Virtual Hardware Operating System for the Xilinx XC6200. Proc. of the International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 1996. 8. Brebner G. The swappable logic unit: a paradigm for virtual hardware. In K. L. Pocek and J. M. Arnold, editors, The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’97). – P. 77–86, Los Alamitos, CA, Apr. 1997. IEEE Computer Society Press. 9. Steiger C., Walder H., Plazner M. Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks // IEEE Transactions on Computers, Vol. 53, № 11. – P. 1393–1407, Noviembre 2004. 10. Göhringer D., Hübner M., Nguepi Zeutebouo E., Becker J. Operating System for Runtime Reconfigurable Multiprocessor Systems // Int. J. Reconfig. Comp. – 2011 (2011). 11. Chen Y., Hsiung P. (2005) Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC // In: Yang L. T., Amamiya M., Liu Z., Guo M., Rammig F. J. (eds.) EUC 2005. LNCS, Vol. 3824. – P. 489–498. Springer, Heidelberg. 12. Morales-Villanueva A. and Gordon-Ross A. On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs // in Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). – 2013. 13. Lee T.-Y., Hu C.-C., Lai L.-W. and Tsai C.-C. Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems // J. Inf. Sci. Eng. – 2010. – Vol. 26, № 4. – P. 1289–1305. 14. Marconi T., Lu Y., Bertels K. and Gaydadjiev G. Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices // In: Proceedings of International Workshop on Applied Reconfigurable Computing, Architectures, Tools and Applications (ARC 2008), March 26–28, 2008. 15. Kalte H. and Porrmann M. Context Saving and Restoring for Multitasking in Reconfigurable Systems // Proc. of the International Conference on Field Programmable Logic and Applications. – 2005. – P. 223–228. 16. Hiibner M., Schuck C., Kiihnle M., Becker J. New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits // Emerging VLSI Technologies and Architectures, 2006 // IEEE Computer Society Annual Symposium on, 2–3 March 2006. – Р. 6. 17. Becker T., Luk W. Cheung, P. Y. K. Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration // Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on, P. 35–44, 23–25 April 2007. 18. Ichinomiya Y., Usagawa S., Amagasaki M., Iida M., Kuga M., Sueyoshi T. Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams // Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual International Symposium on, P. 241, April 29 2012-May 1 2012. 19. Kalte H., Lee G., Porrmann M., Ruckert U. REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems // Proceedings of 19th IEEE International Symposium on Parallel and Distributed Processing, 2005, 04-08 April 2005. 20. Drahonovsky T., Rozkovec M. and Novak O. Relocation of reconfigurable modules on Xilinx FPGA // Design and Diagnostics of Electronic Circuits Systems (DDECS), 2013 IEEE 16th International Symposium on, P. 175–180. 21. J. van der Veen, Fekete S., Majer M., Ahmadinia A., Bobda C., Hannig F. and Teich J. Defragmenting the module layout of a partially reconfigurable device // In Proc. 2005 Int. Conference on Engieering of Reconfigurable Systems and Algorithms. CSREA Press, 2005. 22. Koester M., Porrmann M. and Kalte H. Relocation and defragmentation for heterogeneous reconfigurable systems // In Proc. Int. Conf. Eng. Reconfig. Syst. Algorithms, 2006, P. 70–76. 23. Stephan Suijkerbuijk and Ben H. H. Juurlink, Implementing Hardware Multithreading in a VLIW Architecture, International Conference on Parallel and Distributed Computing Systems, 2005. 24. Montone A., Santambrogio M. D., Sciuto D. & Memik S. O. (2010). Placement and floorplanning in dynamically reconfigurable FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 3(4), 24. 25. Li Z., Hauck S. Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. FPGA 2002: 187–195. 26. Partial Reconfiguration Controller v1.0. LogiCORE IP Product Guide. Vivado Design Suite. PG193 April 1, 2015. [Електронний ресурс]. – Режим доступу: http://www.xilinx.com/support/documentation/ip_documentation/ prc/v1_0/pg193-partial-reconfiguration-controller.pdf. 27. Шеховцов В. А. Операційні системи. – К.: Видавнича група BHV, 2005. – 576 с. 28. Мельник А. О., Архітектура комп'ютера. – Луцьк: Волинська обласна друкарня, 2008. – 470 с. 29. Huang C. H. and Hsiung P. A. Software-controlled dynamically swappable hardware design in partially reconfigurable systems // EURASIP J. on Embedded Systems, Vol. 2008. – P. 231940, 2008. 30. Puttegowda K., Lehn D. I., Park J. H., Athanas P. and Jones M. Context switching in a run-time reconfigurable system // The J. of Supercomputing. – 2003. – Vol. 26. – P. 239–257. 31. Krasteva Y. E., de la Torre E., Riesgo T., Joly D. Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems // Field Programmable Logic and Applications, 2006. FPL'06. International Conference on. – 28–30 Aug. 2006. – P. 1–4. 32. Beckhoff C., Koch D., Torresen, J. Go Ahead: A Partial Reconfiguration Framework // Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual International Symposium on. – April 29 2012–May 1 2012. – P. 37–44.