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  4. Multiplier realization in FPGA of the high level Galois fields.

Multiplier realization in FPGA of the high level Galois fields.

CSN.
2017;
, Number 881
: pp. 41 - 47
https://doi.org/10.23939/csn2017.881.041

Zholubak I. Multiplier realization in FPGA of the high level Galois fields / I. Zholubak, V. Hlukhov // Visnyk Natsionalnoho universytetu "Lvivska politekhnika". Serie: Kompiuterni systemy ta merezhi. — Lviv : Vydavnytstvo Lvivskoi politekhniky, 2017. — No 881. — P. 41–47.

Authors:
  1. Valerii Hlukhov
  2. Ivan Zholubak
1
Lviv Polytechnic National University, Department of Electronic Computing Machines
2
Lviv Polytechnic National University, Ukraine

In this paper, the implementation of matrix multipliers of the Galois fields with basics 2, 3, 5, 7, 13 and the analysis of the implementation of multipliers with a higher basis on the FPGA Xilinx Spartan-6 and Altera – Cyclone-5 is considered. It is shown that the smallest hardware costs will be in multiples of Galois fields with a base 2. For the implementation of the Guild cells with a large foundation, the core generator of the modified Guild cells was implemented.

Galois fields GF (dm)
multiplier
modified Guild cell
LUT
nucleus generator
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