structural complexity

The article proposes methods for improving the structures of multi-bit multipliers, which are characterized by increased speed, reduced structural complexity of the device and reduced structural complexity of inputs and outputs depending on the bit multipliers (512-2048 bits), respectively (1024- 4096) times, compared with known multipliers based on classic single-digit full adders. Optimization of structures of multi-bit multipliers is offered. Comparative estimates of structural, functional and relative functional and structural complexities of their circuit implementations are given.

This paper is suggested the methods of improving the structures of high-speed single-bit and multi-bit binary adders with extremely high speed and minimal hardware complexity are proposed. It is proposed to simplify the structure of the logical element “Exclusive OR" by implementing on the basis of the logical element “Exclusive AND". Improved structures of single-digit incomplete adders based on the logic element “Exclusive AND" are proposed.

Calculating structural complexity of Galois fields multiplier based on elementary converters is analyzed in paper. Structural complexity is determined by combing VHDL- SHmodels into a VHDL-SH model. Mastrovito multiplier and classic Galois fields multiplier were chosen for calculation results analysis. The order of the Galois field, which is considered in the article is ≤ 409.

The structural complexity of multipliers in polynomial basis for Galois field GF(2^m) is analyzed in paper. Mastrovito multiplication algorithm was chosen to determine the structural complexity of multiplication in Galois fields. The definition of structural complexity is calculated by combining the SH- and VHDL-models into a VHDL-SH model.

The article describes the results of evaluation of structural complexity of multi-section binary Galois fields elements multipliers. Elements of the fields are presented in the normal basis of type 2. The order of the field reaches 998. The hardware complexity multipliers allows to implement them on the FPGA. But because of the large structural complexity for certain combinations of the order of the field and the number of sections it is impossible. To identify ways to reduce structural complexity it and its components in main multiplier element – the multiplier matrix are estimated.