At present, distributed control and management systems are becoming increasingly complex, with the number of Internet of Things devices and wireless sensors steadily growing. All of them require the development and improvement of simple and efficient devices for performing computational operations near sensors in real time.
This paper analyzes the use of number-pulse functional converters with variable bit width for computational operations near the sensitive elements of smart sensors in distributed real-time control systems. The key advantages of such devices are their simplicity, reliability, and energy efficiency. The introduction of feedback allows for a comprehensive improvement of the converters' characteristics. Basic structural elements with positive and negative feedback are known, and they exhibit certain differences among themselves.
Numerous studies and analyses of the obtained results for various functions (inverse proportional, logarithmic with different bases, square root, division devices, and others) offer new approaches to creating more advanced structures. This proposed work continues earlier research in the field of number-pulse information processing devices. However, unlike previous publications, it focuses on improving the mathematical principles underlying the computational process and the structural organization of such devices. The study covers aspects of the creation and investigation of combined feedback.
To address the identified problem, the method based on a new approach to combining measurement converter circuits with positive and negative feedback has been improved to enhance metrological characteristics. Additionally, a refined mathematical model with combined feedback has been developed, which has enabled a twofold improvement in calculation accuracy at the beginning of the conversion range.
The proposed methods and tools for performing arithmetic operations and elementary mathematical functions can serve as fundamental computational components for various cases of functional signal conversion in the form of number-pulse codes. These signals can be received from primary measurement sensors or special modeling devices with frequency or number-pulse outputs in real time.
The principle of variable bit width for building such devices enables easy scaling of the bit width of structural elements to extend the dynamic range of the input code within any specified limits.
1. Zhou, F., & Chai, Y. (2020). Near-sensor and in-sensor computing. Nature Electronics, 3(11), 664 671. https://doi.org/10.1038/s41928-020-00501-9
https://doi.org/10.1038/s41928-020-00501-9
2. Faraji, S. R., Najafi, M. H., Li, B., Bazargan, K., & Lilja, D. J. (2019). Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing, In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 1757-1762. https://doi.org/10.23919/DATE.2019.8714937
https://doi.org/10.23919/DATE.2019.8714937
3. Kaining, H., Warren, J. G., & Junchao, W. (2019). Bit-wise iterative decoding of polar codes using stochastic computing. IEEE Transactions on Signal Processing, 67(4), 1138 1151. https://doi.org/10.1109/TSP.2018.2890066
https://doi.org/10.1109/TSP.2018.2890066
4. Najafi, M. H., Faraji, S. R., Bazargan, K., & Lilja, D. (2020). Energy-efficient pulse based convolution for near-sensor processing. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1 5. https://doi.org/10.1109/ISCAS45731.2020.9181248
https://doi.org/10.1109/ISCAS45731.2020.9181248
5. Asadi, S., & Hassan, N. M. (2019). Context-aware number generator for deterministic bit-stream computing. In Proceedings of the IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, NY, USA, 2019, 140-140. https://doi.org/10.1109/ASAP.2019.00-12
https://doi.org/10.1109/ASAP.2019.00-12
6. Chen, K., Chen, T., & Wei, C. (2019). Novel pulse-based analog divider with digital output. IEEE Solid-State Circuits Letters, 3, 21 24. https://doi.org/10.1109/LSSC.2019.2959778
https://doi.org/10.1109/LSSC.2019.2959778
7. Flores, D., Dallet, D., Vladimirescu, A., Cathelin, A., & Deval, Y. (2023). High-resolution fractional digital frequency divider using a binary-rate multiplier. In Proceedings of the 21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 1-5. https://doi.org/10.1109/NEWCAS57931.2023.10198118
https://doi.org/10.1109/NEWCAS57931.2023.10198118
8. Flores, D., Cathelin, A., & Deval, Y. (2023). Fractional frequency synthesizer using a bit-rate-multiplier. U.S. Patent Application No. xxxx, filed on 30 June 2023.
9. Stakhiv, R. I., & Maksymovich, V. M. (2005). Digital two-level synthesizer on a drive on two combinational adders with elimination of unevenness of output pulses. Collection of Scientific Works of the Ukrainian Academy of Printing, Computer Technologies of Printing, 13, 227 234.
10. Garasymchuk, O. I., Dudykevich, V. B., Maksymovich, V. M., & Smuk, R. T. (2004). Generators of test pulse sequences for dosimetric devices. Bulletin of Lviv Polytechnic University: Heat Power, Environmental Engineering, Automation, 506, 187 193.
11. Shkil, A. S., Larchenko, L. V., & Larchenko, B. D. (2020). Bit-stream power function online computer. In Proceedings of the 18th IEEE East-West Design & Test Symposium, Varna, Bulgaria, 423 428. https://doi.org/10.1109/EWDTS50664.2020.9224764
https://doi.org/10.1109/EWDTS50664.2020.9224764
12. Larchenko, B., & Kuznichenko, T. (2021). Mathematical model of bit-stream online computer of irrational functions. In Proceedings of the 15th International Scientific and Practical Conference on Innovation in Science and Technology, Boston, USA, 82 86.
13. Chelebaev, S. V., & Chelebaeva, Y. A. (2016). Converters structures synthesis of time-and-frequency signals parameters in the code of two variables on the radial basis network. In Proceedings of the 5th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, 339 342. https://doi.org/10.1109/MECO.2016.7525776
https://doi.org/10.1109/MECO.2016.7525776
14. Safyannikov, N. M., & Bureneva, O. I. (2020). Time-to-voltage converters based on the time-sharing principle. IEEE Access, 8, 17442 17453. https://doi.org/10.1109/ACCESS.2020.2966023
https://doi.org/10.1109/ACCESS.2020.2966023
15. Bureneva, O. I. (2017). Stream tracking devices for soft measurements implementation. In Proceedings of the 20th IEEE International Conference on Soft Computing and Measurements, (SCM), St. Petersburg, Russia, 2017, 614-616. https://doi.org/10.1109/SCM.2017.7970666
https://doi.org/10.1109/SCM.2017.7970666
16. Gulin, A., Safyannikov, N., Bureneva, O., & Kaydanovich, A. (2018). Assurance of fault-tolerance in bit-stream computing converters. In Proceedings of the 16th IEEE East-West Design & Test Symposium (EWDTS), Kazan, Russia, 418 421. https://doi.org/10.1109/EWDTS.2018.8524812
https://doi.org/10.1109/EWDTS.2018.8524812
17. Stakhiv, M. Y. (2013). Digital functional converters of the spreading type with improved characteristics. Dissertation abstract, Lviv: National University "Lviv Polytechnic."
18. Dudykevich, V. B., Maksymovich, V. M., & Moroz, L. V. (2011). Number-pulse functional converters with pulse feedback. Lviv: National University "Lviv Polytechnic."
19. Baran, R. D., & Dudykevich, V. B. (2024). Hardware implementation of CHIFP with variable bit rate and performance evaluation. Bulletin of the Vinnytsia Polytechnic Institute, 3.
20. Baran, R. D., Maksymovych, V. M., & Garaniuk, P. I. (2008). Criteria of technological feasibility of implementation of CHIFP. Computer Engineering and Information Technologies, 1(3).
21. Baran, R. (2024). Structural and topological features of CHIFP with variable responsibility taking into account their speed. In Proceedings of the International Scientific and Practical Conference on Problems of Computer Science, Software Modeling, and Security of Digital Systems, Lutsk, Ukraine.