The paper analyses the system characteristics and functional capabilities of multi-bit pyramidal adders that can be used in the structures of discrete perceptron of modern neural networks for summing weight coefficients and input signals. The methodology for designing multi-bit adders using flow and spatial-temporal graphs is described. Algorithmic and recursive pyramidal adders have been developed and their main system characteristics have been determined. Software models of multi-bit algorithmic and recursive pyramid adders have been developed using the VHDL hardware description language. Functional modelling and synthesis of developed structures of multi-bit pyramidal adders on FPGA were performed. It has been established that when using multi-bit numbers (n=1024), the hardware complexity of recursive pyramidal adders is reduced by 64 times.
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