Testing of digital circuits by cyclic codes

2017;
: pp.78-82
1
Vinnytsia National Technical University
2
Vinnytsia National Technical University

The application of error correction coding theory to the tasks of technical diagnostics is considered. Known methods of testing based on signature analysis allow detecting only the faults in the digital circuit under test (CUT). The purpose of the research is to provide the possibility of an exact localization of the faults in logic subcircuits within the CUT. In the proposed method, a full test T for testing the CUT is subdivided into an input test T1 (supplied to the inputs of the CUT) and an output test T2 of the expected signatures (recorded into a memory block). Tests T1 and T2 are interpreted as a set of information words and a set of check words of the cyclic Hamming code respectively and are generated by the encoder. The decoder decodes words from both tests simultaneously and searches for errors only in the test T1. As a result, full burst errors in the information words of error correcting code are corrected, which is equivalent to the exact localization of the faults within the CUT.

  1. E. Dubrova, Fault Tolerant Design: an Introduction. Boston, USA: Kluwer Academic Publishers, 2008.
  2. C. Shannon, A mathematical theory of commu­nication. Bell Syst. Tech. J., vol. 27, pp. 379–423, 623–656, 1948.
  3. M. Gavrilov, “Structural redundancy and functional reliability of switching units”, in Proc. First World Congress IFAC, vol. 3, Moscow, USSR: Academy of Science, 1960. (Russian).
  4. L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures Design for Testability. New York, London: Morgan Kaufmann Publishers, 2006.
  5. A. Babitha and S. Divya. “Modified Hamming Codes with Double Adjacent Error Correction along with Enhanced Adjacent Error Detection”, International Journal of Innovative Research in Computer and Communication Engineering, vol. 3, issue 8, pp.7706-7713, Aug. 2015.
  6. E. Fujiwara, Code Design for Dependable Systems.Theory and Practical Applications. USA: John Willy & Sons, Inc., 2006.
  7. V. Semerenko, “Burst-Error  Correction for  Cyclic Codes”, in Proc. Int. IEEE Conference EUROCON-2009, S. Petersburg, Russia: May 2009, pp. 1646–1651. ​
    DOI: 10.1109/eurcon.2009.5167864
  8. X. Tang and S. Wang, “A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips”, IEEE Transactions on Computers, vol. 59, no. 10, pp. 1309 –1319, October 2010.
  9. V. Semerenko, “Parallel Decoding of Bose-Chaud­huri-Hocquenghem Codes”, Engineering Simulation, vol. 16, no. 1, pp. 87-100, Jan.1998.
  10. V. Semerenko, “Estimation of the correcting capability of cyclic codes based on their automation models”, Eastern-European Journal of Enterprise Technologies, no. 2/9 (74), pp. 16–24, 2015. (Russian).
  11. A. Neale and M. Sachdev, “A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory”, IEEE Trans­actions on Device and Materials Reliability, vol. 13, no. 1, pp. 223, 230, March 2013.